ELECTRONICS & SEMICONDUCTORS

Semiconductor process recipes

Task and verification

Sequence chemical vapor deposition (CVD), plasma etch, and rapid thermal anneal steps so a kinetic transport simulator matches wafer thickness, profile, and dopant metrology targets.

Tools and runtime

Kinetic transport simulators + metrology target verifiers

OPENENV / FAB-SIM

Plan a training run

Check the environment’s availability, compatible models and compute in Studio. A catalog entry does not guarantee that hosted training is enabled for your workspace.