ELECTRONICS & SEMICONDUCTORS

Chip physical design (RTL-to-GDSII)

Chip physical design (RTL-to-GDSII) is an OpenEnv-compatible reinforcement learning environment in our Electronics & Semiconductors catalog. An agent acts through the tools below, and a deterministic verifier scores every episode, so the reward can be used for GRPO or other RLVR post-training.

Task and verification

Execute full automated floorplanning, placement, clock tree synthesis, and routing for open ASIC designs. Timing closure, setup/hold slack, and foundry DRC/LVS verify the final GDSII.

Tools and runtime

OpenROAD + OpenSTA + KLayout + Magic DRC/LVS

OPENENV / GDSII

Related Electronics & Semiconductors gyms

• Verilog RTL design & verification
• SKY130 analog IC design
• KiCad PCB layout & routing
• Power electronics & converter design
• DFT & ATPG fault coverage
• DSP & digital communications
• RF & antenna impedance matching
• Electromagnetic & motor design
• Semiconductor process recipes
• Automated instrument calibration (PyVISA)
• Embedded firmware & safety drivers

See how these environments are run privately on the custom RL environments page, and how their rewards are made hard to game in our verifier design guide.

Plan a training run

Check the environment’s availability, compatible models and compute in Studio. A catalog entry does not guarantee that hosted training is enabled for your workspace.