ELECTRONICS & SEMICONDUCTORS

Chip physical design (RTL-to-GDSII)

Task and verification

Execute full automated floorplanning, placement, clock tree synthesis, and routing for open ASIC designs. Timing closure, setup/hold slack, and foundry DRC/LVS verify the final GDSII.

Tools and runtime

OpenROAD + OpenSTA + KLayout + Magic DRC/LVS

OPENENV / GDSII

Plan a training run

Check the environment’s availability, compatible models and compute in Studio. A catalog entry does not guarantee that hosted training is enabled for your workspace.